In this work, a new optimization technique for transistor sizing and a concept of reconfigurable adaptive switches has been introduced to maximize the extracted power. A control unit is designed for adaptive reconfiguration of the switches. These proposed techniques are validated for linear charge-pump topology in UMC 180nm technology.
另一方面，对于180nm或者更加先进的工艺，信号完整性（signal integrity, SI）分析成为必不可少的步骤。 人们知道，在CMOS电路的翻转过程除了受信号上升或下降时间(transition time,也称作slew rate)快慢有关之外，与其栅极的阈值(threshold voltage)极其相关。
Jul 29, 2019 · Analog/mixed-signal and specialty foundry X-Fab has announced that its high-voltage 180nm CMOS semiconductor process, XH018, is now available for automotive applications. These chips will be manufactured at X-Fab’s production facility in Corbeil-Essonnes, France.
May 24, 2020 · 就在前天，Cadence发了款TSMC 7nm的超高速112G/56G 长距离SerDes,用于云数据中心和光网络芯片，5G基础设施的核心IP。 SMIC14nm的10G多协议PHY IP也是他们独家的，5月14日发布的。
Here's how Tsmc is used in Layout Designer jobs: Worked on process node ranging from Samsung 14lpp to TSMC 28nm, 45nm, 65nm. Worked on HIGHLY INTEGRAED LCD VIDEO PROCESSOR (TW8836 and TW8834) using TSMC0.18UM process. Mixed Signal Layout Design for TX and RX blocks in 65nm TSMC process.
Instead of shifting from 180nm to 130nm, TSMC's offered a 150nm half-node. Between 130nm and 90nm there was a 110nm node; between 90nm and 65nm, an 80nm node, between 65nm and 45nm, a 55nm, etc. Samsung Fab Line.
180nm RF LDMOS and 55nm RF EDNMOS – Both structures have pitch <1µm and: – R sp < 0.95 mOhm mm 2, BV ds >10.5V, fT>50 GHz (>10x HB WiFi ) – Ideal PowerSoc implementation scenarios: • 180nm RF LDMOS – 5V SMPS - 2.3X lower P diss, 75% lower gate driver loss • 55nm RF EDMOS – IoT platform with integrated RF, MCU, memory and control –
TSMC 0.18‐μm CMOS process and it can operate at 100‐MHz processing rate. Compared with previous designs, this design achieved higher performance, higher security, higher reliability, more functions, more flexibility, higher compatibility and lower cost than previous designs.